R&D Team Leader
July.2026 - presentBAUM Design Systems, Korea
- Leading the R&D team for commercial EDA tool development.
Minjae Kim
EDA Tool Developer
Career Profile
Minjae Kim received the B.S. degree in Electrical Engineering (Major) and Computer Science Engineering (Minor) from Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea in 2022, and the M.S. degree in Electrical Engineering from Pohang University of Science and Technology (POSTECH), Pohang, South Korea in 2024. His research was conducted with Prof. Seokhyeong Kang in CAD & SoC Design Lab..
During his M.S. program, he was a visiting scholar at the ABK Group, UCSD (University of California, San Diego) from June 2023 to February 2024, where he worked primarily on 3D IC placement — prototyping a multi-die manager — and contributed to the open-source EDA platform OpenROAD.
He is currently an R&D Team Leader at BAUM Design Systems, specializing in design and development of EDA tools. He continues to contribute to OpenROAD as dev-minjae — most recently a Kokkos-based GPU acceleration of the global placer, achieving a 6x speedup while remaining bit-identical to the CPU path when GPU is disabled.
Experience
Engineer
Feb.2024 - July.2026BAUM Design Systems, Korea
- Developed core components of the power model generation flow.
- Built the in-house SystemVerilog parsing layer.
- Implemented an RTL-to-gate elaborator feeding the gate-level analysis flow.
- Implemented a native Liberty parser, validated over an expanded test corpus.
- Led development of a sequential equivalence checker built on the ABC proof engine, certifying clock-gating insertion, retiming, and register merging as behavior-preserving.
- Built and owned the multi-OS packaging and release pipeline (RHEL / AlmaLinux / CentOS) and the regression, nightly, and code-quality CI infrastructure.
- Developed an MCP server exposing the toolchain to LLM agents, with an evaluation harness for regression tracking.
Open-Source Contributor
Feb.2024 - presentOpenROAD Project (github.com/dev-minjae)
- GPU acceleration of the Nesterov-based global placer using Kokkos (54 files, ~8.6K lines): 6x speedup on an RTX 5090, with the CPU path left bit-identical when GPU support is disabled.
- Contributed agent skills (fix-bug / add-test / review-pr) to the project’s development workflow.
Visiting Scholar
June.2023 - Feb.2024ABK Group, UCSD (University of California, San Diego)
- Worked primarily on 3D IC placement: developed a multi-die manager prototype (partitioning, legalization, timing, routing) — handed off for continued development.
- Contributed to the OpenROAD project: implemented RUDY (Routing Utilization estimation with heatmap visualization) and odb exception handling for multi-block designs.
Hardware Develop Team Leader
June.2020 - September.2021Startup Do:main, Gang-Nam in Korea
- Developed medical EEG equipment: full-cycle hardware from circuit design (ADS1299) through PCB fabrication to firmware development.
Undergraduate Research Intern
June.2019 - December.2019Bio-inspired Advanced Sensors Lab (BIAS), UNIST in Korea
- Cadence Virtuoso analog circuit design & verification.
- Implementation of DAC chip protocol with Verilog & UI for ADC application.
Undergraduate Research Intern
February.2019 - August.2019Brain Computer Interface Lab (BCI), UNIST in Korea
- Analyzed realtime EEG data with CNN.
Undergraduate Research Intern
November.2018 - March.2019Institute for Basic Science (IBS), UNIST in Korea
- Data mining for Microglia cell migration.
Education
M.Sc in Electrical Engineering
Feb.2022 - Feb.2024Pohang University of Science and Technology, Republic of Korea
Advisor: Prof. Seokhyeong Kang
BSc in Electrical Engineering (Major) & Computer Science Engineering (Minor)
Mar.2017 - Feb.2022UNIST (Ulsan National Institute of Science and Technology), Republic of Korea
Publications
- TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path 6th ACM/IEEE International Symposium on Machine Learning for CAD (MLCAD), 2024.
- Open-Source 3D Global Placer with D2D Vertical Connections using Louvain Clustering and RePlAce Korean Conference on Semiconductors (KCS), 2023
- RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization, IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE), 2023
Awards
- POSTECH Fellowship May.2022
- Best Award in Naver X Like Lion Hackathon November.2018
Skills
- C++ & C (GCC, gdb, GTest, Valgrind, Intel VTune, clang-tidy)
- Python (PyTorch, PyQt6, automation)
- CUDA & GPU Computing (Kokkos, Nsight, CPU/GPU parity verification)
- CI/CD (Jenkins, CTest, JUnit/Allure, Docker, multi-OS matrix build)
- Build System (CMake, CPack, CTest, Bazel, multi-OS packaging pipeline)
- Embedded (STM32, FPGA, ESP32, Arduino, RaspberryPi)
- HW Design (OrCAD, PSpice, LTspice, Virtuoso, PCB design & fabrication)
- Peripheral & Protocol (SPI, I2C, UART, GPIO)
- Tcl
- Verilog
- EDA (Cadence Innovus, Yosys, OpenROAD)
- Linux System Administration (RHEL, CentOS, Ubuntu, node operation)
- LLM Infrastructure (vLLM, on-premise serving, DGX Spark)
Languages
- KoreanNative
- EnglishAdvanced
Interests
- Electronic Design Automation
- CI/CD & Build Infrastructure
- Embedded Systems & Hardware Design
- Machine Learning